Synopsys Recruitment 2018 for Graduate freshers in Hyderabad – Apply Online

Synopsys Recruitment 2018 for Graduate freshers in Hyderabad – Apply Online. Synopsys job openings 2018 for Technical intern position in Hyderabad. The candidate will be responsible for validation of Emulation tool. The Engineer will also design and develop tests in VHDL/Verilog/System Verilog languages to validate the tool. Interested candidates can apply online through below provided link. please read carefully before applying for this recruitment.

Synopsys Company Profile:

Synopsys, Inc., an American company, is the leading company by sales in the Electronic Design Automation industry. Synopsys’ first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit. Products include logic synthesis, behavioral synthesis, place and route, static timing analysis, formal verification, hardware description language (SystemC, SystemVerilog/Verilog, VHDL) simulators as well as transistor-level circuit simulation. The simulators include development and debugging environments which assist in the design of the logic for chips and computer systems. In recent years Synopsys has also expanded into the application security market, now offering solutions for testing custom and open source code or building holistic security programs.

 

Synopsys Recruitment 2018 Details:

Company: Synopsys

Website: www.synopsys.com

Job Location: Hyderabad

Qualification: B.Tech, M.Tech

Role: Intern Technical Engineer

Experience: 0-2 Years

Type of Industry: IT/Software

Pay or Salary: Not Disclosed by Recruiter

Job Description:

• Seeking a highly motivated and innovative engineer. Working as part of a highly experienced emulation team, the candidate will be contributing towards improving the quality of Synopsys Synthesis and Emulation tools.
• The position offers an excellent opportunity to work with an expert team of Synthesis and emulation engineers responsible for qualifying the FPGA synthesis tool from specification development to performing functional and performance tests for validating the Synthesis and Emulation tool.
• In addition, this is a great opportunity to work with a wide suite of in-house digital design and verification tools, including VCS, Design Compiler.

Responsibilities:

• The candidate will be responsible for validation of Emulation tool.
• The Engineer will also design and develop tests in VHDL/Verilog/System Verilog languages to validate the tool.
• Responsible for analyzing benchmarks & in-house, modifying block-level test benches, executing verification plans, debugging RTL and gate-level simulation failures, performing gate-level simulations, interacting with R&D and CAE teams.

Requirements:

• The successful candidate will have B.Tech / M. Tech with 0-2 years of digital design experience in the industry and hands-on experience in emulation/simulation. Knowledge on areas like Synthesis, simulation, verification, place and route, design reuse and/or physical design is preferred.
• Knowledge and experience on Hardware emulation tool or experience in verification technology, testcase creation, simulation using VCS or other simulators, debugging with Verdi/DVE, familiarity with scripting languages is a plus along with good organization and communication skills for interacting with R&D and CAEs teams.

Click Here For Apply Online

The post Synopsys Recruitment 2018 for Graduate freshers in Hyderabad – Apply Online appeared first on Walkin2day.

from Walkin2day https://ift.tt/2H3kIcP